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PD -97371 IRLS4030-7PPBF Applications l DC Motor Drive l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Optimized for Logic Level Drive l Very Low RDS(ON) at 4.5V VGS l Superior R*Q at 4.5V VGS l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free G HEXFET(R) Power MOSFET D G S VDSS RDS(on) typ. max. ID D 100V 3.2m 3.9m 190A S G S S S S D2Pak 7 Pin D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Parameter Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery e Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw Max. 190 130 750 370 2.5 16 13 -55 to + 175 300 10lbxin (1.1Nxm) 320 See Fig. 14, 15, 22a, 22b Units A W W/C V V/ns C Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy d Avalanche Current c Repetitive Avalanche Energy f mJ A mJ Thermal Resistance Symbol RJC RJA Parameter Junction-to-Case jk Junction-to-Ambient (PCB Mount) ij Typ. --- --- Max. 0.40 40 Units C/W www.irf.com 1 02/12/09 IRLS4030-7PPBF Static @ TJ = 25C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units 100 --- --- --- 1.0 --- --- --- --- --- Conditions V(BR)DSS Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) IDSS IGSS RG(int) Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance --- 0.10 3.2 3.3 --- --- --- --- --- 2.0 --- --- 3.9 4.1 2.5 20 250 100 -100 --- V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAc m VGS = 10V, ID = 110A f VGS = 4.5V, ID = 94A f V VDS = VGS, ID = 250A A VDS = 100V, VGS = 0V VDS = 100V, VGS = 0V, TJ = 125C nA VGS = 16V VGS = -16V Dynamic @ TJ = 25C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units S nC Conditions VDS = 25V, ID = 110A ID = 110A VDS = 50V VGS = 4.5V f ID = 110A, VDS =0V, VGS = 4.5V VDD = 65V ID = 110A RG = 2.7 VGS = 4.5V f VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 80V h VGS = 0V, VDS = 0V to 80V g 250 --- --- --- 93 140 --- 27 --- --- 43 --- --- 50 --- --- 53 --- --- 160 --- --- 110 --- --- 87 --- --- 11490 --- --- 680 --- --- 300 --- Effective Output Capacitance (Energy Related)h --- 760 --- --- 1170 --- Effective Output Capacitance (Time Related)g ns pF Diode Characteristics Symbol IS ISM VSD trr Qrr IRRM ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) c Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time Min. Typ. Max. Units --- --- --- --- 190 750 A Conditions MOSFET symbol showing the integral reverse G D S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 110A, VGS = 0V f VR = 85V, --- 53 --- ns TJ = 25C TJ = 125C IF = 110A --- 63 --- di/dt = 100A/s f --- 99 --- nC TJ = 25C TJ = 125C --- 155 --- --- 3.3 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.05mH RG = 25, IAS = 110A, VGS =10V. Part not recommended for use above this value . ISD 110A, di/dt 1520A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C. RJC value shown is at time zero. Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994. 2 www.irf.com IRLS4030-7PPBF 1000 TOP VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.7V 2.5V 1000 TOP VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.7V 2.5V ID, Drain-to-Source Current (A) 100 BOTTOM ID, Drain-to-Source Current (A) BOTTOM 100 10 2.5V 2.5V 60s PULSE WIDTH Tj = 25C 1 0.1 1 10 100 1000 V DS, Drain-to-Source Voltage (V) 10 0.1 1 60s PULSE WIDTH Tj = 175C 10 100 1000 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 1000 Fig 2. Typical Output Characteristics 3.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 100 T J = 175C 2.5 ID = 110A VGS = 10V 2.0 10 T J = 25C 1.5 1 VDS = 25V 60s PULSE WIDTH 0.1 1 2 3 4 5 1.0 0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics 100000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd Fig 4. Normalized On-Resistance vs. Temperature 5.0 ID= 110A VGS, Gate-to-Source Voltage (V) 4.0 VDS= 80V VDS= 50V C, Capacitance (pF) 10000 Ciss 3.0 1000 Coss Crss 2.0 1.0 100 1 10 100 1000 VDS, Drain-to-Source Voltage (V) 0.0 0 20 40 60 80 100 120 QG, Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage www.irf.com 3 IRLS4030-7PPBF 1000 T J = 175C 100 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100sec ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 1msec 10 T J = 25C 10 10msec DC 1 Tc = 25C Tj = 175C Single Pulse 1 10 100 1000 1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-to-Drain Voltage (V) 0.1 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 200 180 160 ID, Drain Current (A) Fig 8. Maximum Safe Operating Area 125 Id = 5mA 120 115 110 105 100 95 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C ) 140 120 100 80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (C) Fig 9. Maximum Drain Current vs. Case Temperature 4.0 3.5 3.0 Energy (J) Fig 10. Drain-to-Source Breakdown Voltage 1400 EAS , Single Pulse Avalanche Energy (mJ) 1200 1000 800 600 400 200 0 ID 12A 16A BOTTOM 110A TOP 2.5 2.0 1.5 1.0 0.5 0.0 -20 0 20 40 60 80 100 120 25 50 75 100 125 150 175 Fig 11. Typical COSS Stored Energy VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com IRLS4030-7PPBF 1 Thermal Response ( Z thJC ) C/W D = 0.50 0.1 0.20 0.10 0.05 0.02 0.01 J 0.01 R1 R1 J 1 2 R2 R2 C C Ri (C/W) i (sec) 0.176 0.000343 0.227 0.006073 1 2 0.001 SINGLE PULSE ( THERMAL RESPONSE ) C i= i/R i Ci= i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1 0.0001 1E-006 1E-005 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Duty Cycle = Single Pulse Avalanche Current (A) 100 0.01 0.05 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01 Fig 14. Typical Avalanche Current vs.Pulsewidth 400 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 110A 300 200 100 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) 175 EAR , Avalanche Energy (mJ) 0 25 50 75 100 125 150 Starting T J , Junction Temperature (C) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRLS4030-7PPBF 3.0 VGS(th) , Gate threshold Voltage (V) 30 25 20 IRRM (A) 2.5 2.0 1.5 1.0 0.5 0.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( C ) IF = 75A V R = 85V TJ = 25C TJ = 125C ID = 250A ID = 1.0A 15 10 5 0 0 200 400 600 800 1000 diF /dt (A/s) ID = 1.0mA Fig 16. Threshold Voltage vs. Temperature 30 25 20 IRRM (A) Fig. 17 - Typical Recovery Current vs. dif/dt 1400 IF = 110A V R = 85V TJ = 25C TJ = 125C 1200 1000 QRR (A) IF = 75A V R = 85V TJ = 25C TJ = 125C 800 600 400 200 0 15 10 5 0 0 200 400 600 800 1000 diF /dt (A/s) 0 200 400 600 800 1000 diF /dt (A/s) Fig. 18 - Typical Recovery Current vs. dif/dt 1600 1400 1200 1000 QRR (A) Fig. 19 - Typical Stored Charge vs. dif/dt IF = 110A V R = 85V TJ = 25C TJ = 125C 800 600 400 200 0 0 200 400 600 800 1000 diF /dt (A/s) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRLS4030-7PPBF D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Body Diode Forward Drop Inductor Curent Inductor Current Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V(BR)DSS 15V tp DRIVER VDS L RG VGS 20V D.U.T IAS tp + V - DD A 0.01 I AS Fig 22a. Unclamped Inductive Test Circuit VDS VGS RG RD Fig 22b. Unclamped Inductive Waveforms VDS 90% D.U.T. + - VDD V10V GS Pulse Width 1 s Duty Factor 0.1 % 10% VGS td(on) tr t d(off) tf Fig 23a. Switching Time Test Circuit Current Regulator Same Type as D.U.T. Fig 23b. Switching Time Waveforms Id Vds Vgs 50K 12V .2F .3F D.U.T. VGS 3mA + V - DS Vgs(th) IG ID Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr www.irf.com Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform 7 IRLS4030-7PPBF D2Pak - 7 Pin Package Outline Dimensions are shown in millimeters (inches) 8 www.irf.com IRLS4030-7PPBF D2Pak - 7 Pin Part Marking Information 14 D2Pak - 7 Pin Tape and Reel Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 02/09 9 |
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